1. Field of the Invention
The present invention relates to a bus arbitration interface, and more particularly to a bus arbitration interface in an LSI having a DMA (Direct Memory Access) controller therein or an LSI having a bus master arbitration function.
2. Description of the Related Art
The structure of this kind of the conventional bus arbitration interface is shown in FIG. 4. FIG. 4 shows an example of a bus arbitration interface in an LSI with a DMA controller built therein.
With reference to FIG. 4, an LSI 41 has a DMA controller 42 and a DMA device arbitration interface 45. There is a DMA device 48 for gaining access to the LSI 41 through a DMA device arbitration interface 47, outside of the LSI 41. Assume that the DMA device 48 consists of four devices, although they are not illustrated. Signals to be exchanged between the LSI 41 and the DMA device 48 include a DMA request signal to be transferred from each device to the DMA controller 42, a DMA acknowledge signal to be transferred from the DMA controller 42 to each device, and an operation clock signal of the DMA controller 42.
The LSI 41 permits each DMA device to transfer data by the two signals; the DMA request signal and the DMA acknowledge signal. Therefore, the number (n) of devices in the DMA device 48 requires (n.times.2) signals. One operation clock signal of the DMA controller 42 is further added to them and therefore (n.times.2+1) DMA interface signals are totally required for the LSI 41's access to the DMA device 48. As mentioned above, since FIG. 4 shows an example in the case where the number of devices included in the DMA device 48 is four, the DMA interface signal results in 9 (=4.times.2+1). Therefore, the LSI 41 requires nine I/O pins.
As mentioned above, in the conventional bus arbitration interface, an LSI requires the number of I/O pins in proportion to the number of the DMA devices to be accessed by the LSI. Therefore, the number of I/O pins is increased with a recent inclination to a multifunctional and large-scaled LSI, thereby causing complexity of the LSI structure and high cost.